Chokepoint analysis · August 2026
Where concentration creates durable leverage
Market share alone does not create a chokepoint. A node with 80% concentration but 6-month substitution time has limited coercive leverage. A node with 60% concentration and a 5-year qualification cycle may be strategically decisive. The relevant variables are substitution difficulty, capacity expansion lead time, switching cost, and whether a state actor can actually exercise the concentration as leverage. Each card below also includes a "time to relief" estimate — when announced capacity expansions are likely to produce usable output, using the same method applied to LNG and oil infrastructure elsewhere on this site.
EUV Lithography — ASML
Equipment layer · technology monopoly · Constraint: binding · Durability: very high
Commercial EUV suppliers
1
ASML sole supplier · no commercial alternative
EUV to China
Zero
Controls have held since 2019 · ASML annual report
ASML is the sole commercial supplier of EUV lithography equipment used to manufacture chips at sub-3nm nodes. The concentration is not one building: EUV depends on Carl Zeiss SMT (sole EUV optics supplier), TRUMPF (sole EUV laser supplier), and a specialist supply network built over three decades that no other ecosystem has replicated. EUV systems have never shipped to China. ASML raised 2026 revenue guidance to €43–45B (~19% above prior midpoint), with SK Hynix placing a $7B+ multi-year EUV order for HBM expansion alone. The chokepoint is the technology ecosystem, not a single facility.
Time to relief
No relief visible. China cannot replicate EUV at commercial yields on any known timeline. DUV multi-patterning is technically viable for older nodes but cannot replicate EUV economics at the frontier. ASML itself is supply-constrained — raising production capacity 30% per year to meet demand.
Semiconductor Equipment — US-NL-JP
Equipment layer · allied coalition · Constraint: binding · Durability: very high
US equipment firms
Applied, Lam, KLA
Deposition · etch · inspection · metrology
Japan equipment
Tokyo Electron
Coater/developer · etch · CVD
The semiconductor equipment chokepoint is not located in one Dutch monopoly. It is distributed across a US-Dutch-Japanese equipment ecosystem that is the real foundation of export control effectiveness. Applied Materials, Lam Research, and KLA dominate deposition, etch, and inspection respectively — all subject to BIS jurisdiction. Tokyo Electron (Japan) is the primary coater/developer and etch tool supplier. Allied coordination between these three jurisdictions is what makes controls meaningful. A gap in any one partner creates a circumvention pathway. Japan's October 2023 export control expansion covering 23 categories of chip-making equipment was essential to closing this gap.
Time to relief (for China)
Partial and slow. China's domestic equipment industry (NAURA, AMEC, SMEE) is making real progress at mature nodes. Advanced-node deposition and etch remain dependent on foreign equipment at competitive yields.
Advanced Packaging — CoWoS
Assembly layer · Constraint: binding · Durability: high
Taiwan adv. packaging share
~85%
Silicon Analysts March 2026 (confidence: moderate — sell-side estimate)
CoWoS lead time
50–78 weeks
Silicon Analysts June 2026 · both CoWoS-S and -L fully booked
Advanced packaging is where GPU dies are integrated with HBM into functional AI accelerators. Epoch AI data shows leading AI chip designers accounted for ~90% of global CoWoS and HBM supply in 2025 while consuming only 12% of advanced logic die production — packaging, not wafer production, has been the binding constraint since 2025. Nvidia reportedly holds approximately 60% of 2026 CoWoS wafer capacity; the top three customers account for an estimated >85% (Silicon Analysts, June 2026 — sourced from sell-side; treat as directional). Ajinomoto holds a dominant position in ABF substrate film used in advanced packages, with AI server racks consuming approximately 10× more ABF than standard PCs.
Time to relief
TSMC committed $265B total to US manufacturing and is expanding CoWoS. New CoWoS capacity: facility construction → equipment installation (~18mo) → customer qualification (~6–12mo) → volume ramp. Realistic capacity relief: late 2026 at the margin, meaningful relief 2027–2028. Demand is also expanding — relief may be partial.
High-Bandwidth Memory — HBM
Memory layer · Constraint: tight · Durability: high
SK Hynix HBM share
~53%
Silicon Analysts July 2026 · Samsung ~35% · Micron ~11%
2026 supply status
Sold out
All three vendors · non-cancellable contracts through 2026; 2027 also booked
The entire global HBM supply from all three producers is allocated under non-cancellable contracts through 2026, with 2027 already booked. Contract DRAM prices spiked +90–95% QoQ in Q1 2026 — the largest single-quarter spike on record per TechTimes. SK Hynix CEO has publicly stated 2027 will be "the worst supply shortage in the memory industry's history." The chokepoint is not a monopoly but three-player extreme concentration, with ~18–24 month capacity expansion timelines, mandatory co-qualification with Nvidia/AMD/Google platforms, and HBM4E yield uncertainty (12-stack downgrade to 8-stack under evaluation for Rubin Ultra per Silicon Analysts, August 2026). HBM4 yield at SK Hynix and Samsung reported at ~80% as of August 2026 — a significant improvement from <60% at launch (Silicon Analysts; treat as directional).
Time to relief
SK Hynix +54 trillion KRW (~$39B) across Y2 and M17 fabs: Y1 initial production Feb 2027 → M17 Dec 2028 → Y2 Jun 2029, each with 12–18 month yield ramp. Meaningful supply relief at scale: 2028–2029. China's CXMT targeting HBM3 by end-2026 — 2–3 generations behind current frontier.
Leading-edge foundry — TSMC
Logic layer · Constraint: tight · Durability: high
TSMC adv. logic share
~70–90%
70% pure-play foundry revenue · ~90% advanced foundry sub-7nm · Counterpoint Q3 2025 · denominator matters — see text
2nm booking status
Booked into 2028
New 3nm kickoffs suspended · TSMC investor briefings
TSMC controls approximately 90% of advanced foundry capacity at sub-7nm nodes — meaning chips manufactured for external customers at leading-edge nodes (Counterpoint Research Q3 2025; Economy Insights March 2026). This figure excludes integrated device manufacturers (Samsung, Intel) producing for their own designs, and excludes DRAM/NAND. Within the narrower category of AI accelerator foundry production, TSMC's share is even higher. Taiwan-based companies account for ~67% of total foundry revenue. TSMC's 2nm node is fully booked well into 2028; new 3nm project kickoffs have been suspended with customers steered toward 2nm. TSMC's strategic significance is primarily about Taiwan's vulnerability, not Taiwan's leverage — TSMC does not deploy its market position as a unilateral foreign policy instrument. A Taiwan contingency would simultaneously disrupt every AI hardware program globally.
Time to relief
TSMC Arizona Fab 21: Phase 1 (4nm) in volume production 2025; Phase 2 (3nm/2nm) targeted H2 2027. Arizona covers an estimated <5% of Taiwan's advanced-node capacity (denominator: advanced-node wafer starts — precise figure not publicly disclosed). Samsung 2nm and Intel 18A offer alternative paths at 12–18 month customer qualification timelines.
EDA software & IP — Synopsys, Cadence, Arm
Design layer · Constraint: binding (for China) · Durability: very high
US EDA market share
>90%
Synopsys · Cadence · Mentor/Siemens EDA · BIS jurisdiction
Arm architecture
UK/US
Licenses to virtually all mobile and data-center chip designers
EDA is a different kind of chokepoint: not physical scarcity but switching cost and ecosystem lock-in. Switching EDA tools requires redesigning entire chip development flows, rebuilding process design kit integrations, and retooling verification — measured in years. BIS export controls on EDA for advanced node chip design in China are in effect. Arm's architecture underpins nearly all mobile and many data-center processors globally, with Arm subject to US jurisdiction. The relevant question is whether the switching cost remains prohibitive as China builds domestic alternatives.
Time to relief (for China)
China's Primarius and Empyrean are viable at mature nodes. RISC-V ecosystem is actively building. Advanced-node EDA gap: likely 5+ years to competitive parity. This is the longest substitution timeline in the stack after EUV.
Power, grid & data-center infrastructure
Infrastructure layer · Constraint: non-binding today · Durability: growing
US data center power by 2030
9.5–15%
of US electricity · Berkeley Lab 2025 (range reflects scenario uncertainty)
Grid transformer lead time
1–2+ years
Industry reports · not responsive to capital on short timelines
Power is not currently a chokepoint in the same sense as HBM or CoWoS — it is not concentrated in a small number of firms or geographies. But CSIS has explicitly described electricity supply as a binding constraint on AI expansion. The bottleneck is not generation capacity in aggregate but grid interconnection timelines, transformer procurement lead times, and permitting — constraints that do not respond to capital the way chip fabs do. If CoWoS and HBM capacity expands substantially through 2027–2028, the constraint that limits frontier AI compute may migrate to megawatts rather than silicon.
Time to relief
Unlike semiconductor nodes, power constraints are geographically distributed. They are also policy-responsive differently — permitting reform, nuclear power restarts, and transmission infrastructure are now AI policy issues. This is where AI industrial policy in 2027–2028 may diverge most sharply from the current export-control focus.
Silicon Analysts March–August 2026 · TSMC investor reports · ASML Q1 2026 earnings · SK Hynix earnings · Santiago & Company June 2026 · Epoch AI 2026 · Berkeley Lab 2025 · CSIS Wadhwani Center · SIA June 2026
Analytical framework
Chokepoint durability matrix
Methodology note — durability ratings
Ratings are qualitative assessments across three dimensions, not mathematical scores. Substitution difficulty: very high = no demonstrated alternative at commercial yields; high = alternatives exist but require 2+ year qualification cycles; moderate = alternatives available with 6–18 month transition; low = commodity-like substitution. Expansion lead time: very high = 5+ years from announcement to usable capacity; high = 2–5 years; moderate = 1–2 years; low = <1 year. Policy controllability: very high = single jurisdiction can restrict; high = requires allied coordination; moderate = controls exist but incomplete; low = not meaningfully controllable. Overall durability is a judgment across all three — not a formula applied to ordinal scores.
A market-share figure does not equal a chokepoint. This matrix tracks the variables that determine whether concentration creates durable geopolitical leverage. Question marks indicate genuine gaps in available evidence — not assumed absence of constraint. Scores are qualitative; the evidence behind each is in the cards above.
| Node | Concentration | Substitution difficulty | Expansion lead time | Policy controllability | Time to relief |
|---|---|---|---|---|---|
| EUV lithography | Very high (100% ASML) | Very high (>10yr) | Long (3–5yr replicate) | High (Dutch+US allied) | None visible |
| Semicon. equipment (US-NL-JP) | Very high (coalition) | High (process qual.) | Long (3–5yr domestic) | High (allied coord.) | Partial, slow |
| EDA software | Very high (>90% US) | Very high (flow rebuild) | N/A (software) | Very high (BIS/EAR) | 5+ years at frontier |
| Advanced packaging (CoWoS) | Very high (~85% TW) | High (18mo facility) | Long (build+qual) | Mixed (Taiwan risk) | Marginal 2026; meaningful 2027–28 |
| HBM memory | High (SK+Samsung 88%) | High (co-qual 18–24mo) | Long (fab+yield ramp) | Mixed (US-ally) | Scale relief 2028–29 |
| Leading-edge foundry | Very high (~90% TSMC) | High (12–18mo qual) | Long (2027–28) | Mixed (Taiwan risk) | Arizona <5% before 2028 |
| Japan materials | Very high (>90% EUV PR) | High (process integration) | Moderate | High (JP export controls) | Slow |
| Power / grid | Low globally | Low (geography-dependent) | Very long (permitting) | Low (distributed) | Policy-dependent |
Silicon Analysts · BIS Federal Register · ASML annual reports · Epoch AI · Santiago & Company · TSMC investor briefings · Berkeley Lab
Four forms of leverage
Not all chokepoints work the same way
A market-concentration chokepoint and a legal-jurisdictional chokepoint operate through completely different mechanisms. Conflating them leads to policy errors — targeting the wrong node, or expecting market leverage to function like legal leverage.
Technology monopoly
ASML / EUV
Sole commercial EUV supplier · Netherlands · Carl Zeiss · TRUMPF
No country can manufacture frontier AI chips without EUV lithography, and only ASML makes it commercially. The coercive instrument is the Dutch state through export licensing — not ASML itself. ASML cannot independently deny or grant access. The chokepoint holds because the technology ecosystem (optics, laser, software) cannot be replicated quickly by any outside actor, and because Dutch export licensing policy is aligned with US and Japanese allied controls.
Manufacturing concentration
TSMC / leading-edge foundry
~90% advanced logic · Taiwan · not a policy instrument
TSMC has market power but Taiwan does not independently deploy TSMC as a foreign policy instrument. The strategic significance of TSMC's position is primarily Taiwan's vulnerability — a military contingency disrupting TSMC disrupts all AI hardware programs simultaneously. This is a risk exposure, not a leverage tool. The mechanism is fundamentally different from ASML's.
Supplier concentration
SK Hynix + Samsung / HBM
South Korea ~88% HBM · structural relevance · not actively wielded
South Korea's HBM concentration creates strategic relevance for US-Korea alliance dynamics. The leverage is structural, not actively exercised. South Korea's position is closer to a potential target of leverage (via US export controls on HBM to China) than an independent source of it. The mechanism: HBM controls require allied cooperation from Seoul, which makes Korea a critical node in any export control coalition.
Jurisdictional leverage
US Bureau of Industry and Security
Export Administration Regulations · foreign-produced direct product rule
BIS can extend US export-control jurisdiction to certain foreign-produced semiconductor items made with specified US technology or equipment when defined destination or end-user conditions are met. Because US tools and software sit deep in the semiconductor production stack, that jurisdiction can reach well beyond goods manufactured inside the United States — but FPDP is not a blanket rule covering every foreign chip containing US technology. It applies through defined product, technology, destination, and end-user conditions. This is why the equipment coalition with the Netherlands and Japan is essential: it extends the coverage perimeter by bringing Dutch EUV and Japanese materials and equipment into a coordinated allied control architecture.
BIS Federal Register · EAR 15 CFR 730–774 · Congressional Research Service R48642
Export control timeline · 2022–2026
How controls moved from chips to the production stack
The trajectory shows a deliberate shift: from restricting access to specific chips toward constraining China's ability to produce advanced chips domestically. Each rule expanded the control perimeter further upstream. The critical insight is that effectiveness depends on allied coordination — US controls are necessary but not sufficient without Dutch EUV restrictions and Japanese equipment and materials controls.
Oct 2022
PERIMETER SHIFT
BIS imposes sweeping chip and equipment controls — largest restriction in a generation
What changed in the control perimeter: from controlling specific chip exports → constraining China's ability to produce advanced chips domestically. Controls covered advanced computing chips (>A100 performance), semiconductor manufacturing equipment, and US-person support for advanced PRC fabs. The foreign-produced direct product rule was substantially expanded to cover items produced using US-origin equipment or software in specified categories.
Oct 2023
LOOPHOLE CLOSED
Updated rules close performance threshold loopholes — anti-circumvention strengthened, country-level controls expanded
What changed: revised chip-performance thresholds to prevent near-controlled designs from substituting for controlled chips. Third-country enforcement of FPDP strengthened to prevent circumvention through intermediaries. Controls extended to 24 additional countries to close transshipment routes.
BIS Federal Register · October 17 2023
Jan 2025
GLOBAL SCOPE
AI Diffusion Rule — first attempt to regulate global access to advanced AI chips and model weights through tiered country framework
What changed: controls moved beyond bilateral US-China restriction toward multilateral global AI governance through export control architecture. Tiered three-category country access framework for advanced AI compute and certain model weights. Represented a significant conceptual shift in how the US conceived of AI export control — from a China-specific policy to a global compute governance tool.
BIS Federal Register · January 13 2025 · CSIS Wadhwani AI Diffusion Rule analysis
Jan 2026
H200 case-by-case licensing framework — managed restriction replaces blanket ban for approved Chinese customers
What changed: BIS moved from blanket H200 restriction to a licensed-export regime for approved Chinese entities with conditions. Annual licence renewal introduces policy uncertainty for supply chain planning — companies previously looking 3–5 years ahead now have a 12-month ceiling on policy certainty. Managed restriction rather than hard decoupling — preserving limited revenue channels for US firms while maintaining strategic leverage.
BIS · Commerce Dept · January 2026 · CSIS semiconductor export control analysis
Mar 2026
Nvidia redirects TSMC CoWoS capacity from H200 to Vera Rubin — export uncertainty reshapes production allocation
What changed: regulatory uncertainty over H200 China approvals caused Nvidia to reallocate constrained CoWoS packaging capacity toward next-generation Vera Rubin chips with confirmed US/allied orders. Illustrates a mechanism beyond enforcement: export control uncertainty itself shapes supply allocation decisions, effectively reducing China's access even before formal rulings. Vera Rubin entered full production May 2026.
Financial Times March 5 2026 · Nvidia Newsroom May 2026 · CNAS "American AI Companies Can't Get Enough Chips" May 2026
2026 ongoing
CHINA RESPONSE
China accelerates domestic stack — Huawei Ascend, CXMT HBM, SMIC 7nm DUV, domestic EDA, RISC-V
What changed: China's substitution strategy is producing real progress at mature nodes and in accelerator design while frontier gaps remain. The policy question is not whether China can substitute everything — it is which specific nodes remain constraining as substitution improves, and at what economic penalty. A DOJ indictment unsealed in 2026 revealed a $2.5B Supermicro server smuggling operation — evidence of persistent unmet demand when legal channels are restricted.
DOJ indictment 2026 · SMIC earnings · Huawei documentation · SemiAnalysis · CXMT reports
BIS Federal Register · CSIS Wadhwani Center · CNAS May 2026 · Financial Times March 2026 · Nvidia Newsroom · Congressional Research Service R48642
China substitution map · August 2026
Where Beijing can substitute — and at what cost
The right question is not whether China is "catching up" as a single number. The relevant variables differ by node: current capability, remaining gap, economic penalty of substitution, and commercial timeline. A technically viable substitute that costs 3× more and yields 40% less is not commercially viable at scale. The analysis below uses these four dimensions for each major node.
Logic foundry (SMIC)
Current capability7nm via DUV multi-patterning
Frontier gap3–4 nodes at leading edge
Economic penaltyHigher cost · likely lower yield
EUV accessNone · controls holding
DUV multi-patterning is technically viable but cannot replicate EUV economics at frontier nodes. The constraint reduces but does not eliminate leverage. Gap is in process economics and yield, not just node designation.
HBM memory (CXMT)
Current targetHBM3 commercial yields 2026
Frontier (SK Hynix)HBM4 at ~80% yield
Generation gap2–3 generations behind frontier
Commercial scaleProgress · not yet confirmed
Real progress in development. HBM3 commercial yields at scale would be significant but still 2–3 generations behind current frontier HBM4/4E. Bandwidth and thermal performance gaps remain at comparable node.
AI accelerator (Huawei Ascend)
Current capabilityViable for many workloads
Frontier gapPerformance gap uncertain at scale
Software ecosystemCUDA moat is largest barrier
Volume constraintSMIC yield limits production
Ascend is a credible alternative for inference workloads. Frontier training constrained by software ecosystem maturity and memory bandwidth. Volume is the current ceiling, not design quality.
EDA & design tools
Current capabilityPrimarius · Empyrean (mature nodes)
Advanced-node EDANot yet commercially viable
RISC-V progressActive ecosystem building
Timeline estimate5+ years at frontier
Longest substitution timeline in the stack after EUV. RISC-V reduces Arm dependency. Advanced-node EDA remains a genuine gap — the switching cost is measured in years of re-tooling, not months.
The substitution cost question
China's substitution strategy does not need to match the frontier to be strategically significant — it needs to be good enough to sustain AI development at sufficient scale and acceptable cost. The policy question is: at what point does the economic penalty of domestic substitution become tolerable relative to China's AI development objectives, and which specific chokepoints remain constraining after that threshold is crossed? That question has a different answer for each node in the stack — and different answers for inference workloads versus frontier training.
SMIC earnings · Huawei technical documentation · SemiAnalysis · DOJ indictment 2026 · CXMT reports · Semiconductors Insight 2026 · Congressional Research Service
Where the constraint migrates
The bottleneck is not fixed — and training ≠ inference
The most important analytical question in AI compute is not which node is constrained today — it is where the constraint migrates as investment responds. CoWoS was not a significant constraint in 2022. It emerged as a major bottleneck by 2025 as chip supply expanded and packaging capacity could not keep pace. The same dynamic is now visible in power infrastructure.
Training vs inference is a critical distinction that most chokepoint analyses collapse. Frontier model training and large-scale inference have different hardware, latency, memory, power, and geographic requirements. A chokepoint critical for training a 1-trillion-parameter model may matter much less for serving 500 million inference requests daily — the hardware, memory bandwidth, and geographic distribution requirements are fundamentally different. "AI compute" is not one market, and treating it as one leads to misidentified policy targets.
Current signals suggest the next constraint migration: as TSMC, SK Hynix, and Micron expand CoWoS and HBM capacity through 2027–2029, and as the AI hardware market fragments across frontier training, inference, and edge deployment, the binding constraint may increasingly be power availability, grid interconnection timelines, transformer procurement, and cooling infrastructure — none of which respond to capital the way chip fabs do, and none of which are concentrated in a small number of countries.
If that migration occurs, the most important AI industrial policy decisions in 2028–2030 may involve permitting reform, transmission infrastructure, nuclear power restarts, and data-center siting — not chip export controls. That reorientation would represent a significant shift in where geopolitical leverage over AI compute actually resides.
Berkeley Lab 2024 US data center energy report · CSIS Wadhwani Center "Powering Innovation" 2026 · Epoch AI compute trends · Santiago & Company June 2026